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As part of today’s AMD’s 2022 Financial Analyst Day, the company is offering a short, high-level update on their forthcoming Zen 4 CPU architecture. This information is being divulged as part of the company’s larger Zen architecture roadmap, which today is being extended to announce Zen 5 for 2024.
The biggest news here is that AMD is, for the first time, disclosing their IPC expectations for the new architecture. Addressing some post-Computex questions around IPC expectations, AMD is revealing that they expect Zen 4 to offer an 8-10% IPC uplift over Zen 3. The initial Computex announcement and demo seemed to imply that most of AMD’s performance gains were from clockspeed improvements, so AMD is working to respond to that without showing too much of their hand months out from the product launches.
This makes up a good chunk of AMD’s overall >15% expected improvement in single-threaded performance, which was previously disclosed at Computex and essentially remains unchanged. That said, AMD is strongly emphasizing the “greater than” aspect of that performance estimate. At this point AMD can’t get overly specific since they haven’t locked down final clockspeeds, but as we’ve seen with their Computex demos, peak clockspeeds of 5.5GHz (or more) are currently on the table for Zen 4.
AMD is also talking a bit more about power and efficiency expectations today. At this point, AMD is projecting a >25% increase in performance-per-watt with Zen 4 over Zen 3 (based on desktop 16C chips running CineBench). Meanwhile the overall performance improvement stands at >35%, no doubt taking advantage of both the greater performance of the architecture per-thread, and AMD’s previously disclosed higher TDPs (which are especially handy for uncorking more performance in MT workloads). And yes, these are terrible graphs.
Finally, AMD is confirming that there will be V-Cache equipped Zen 4 SKUs within their processor lineup. No specific SKUs are being announced today, but AMD is reiterating that V-Cache was not just a one-off experiment for the company, and that they will be employing the die stacked L3 cache on some Zen 4 chips as well.
